In recent years, there has been developed an optical element in which porous silicon is formed to be used as a light emitting element. Japanese Laid-Open Patent Publication No. 4-356977 discloses such an optical element, in which a large number of micro-pores 102 are formed in the surface region of a silicon substrate 101 by anodization, as shown in FIG. 33. If the porous silicon is irradiated with light, photoluminescence having its absorption edge in the visible region is observed, which implements a light-receiving/light-emitting element using silicon. That is, in a normal semiconductor apparatus composed of single-crystal silicon, an excited electron makes an indirect transition to a lower energy level so that the energy resulting from the transition is converted into heat, which renders light emission in the visible region difficult. However, there has been reported a phenomenon that, if silicon has a walled structure, such as porous silicon, and its wall thickness is about 0.01 .mu.m, the band width of the silicon is enlarged to 1.2 to 2.5 eV due to the quantum size effects, so that an excited electron makes a direct transition between the bands, which enables light emission.
It has also been reported that two electrodes are provided on both ends of the porous silicon so that electroluminescence is observed by the application of an electric field.
However, if electroluminescence is to be obtained by the application of an electric field or photoluminescence is to be obtained by the irradiation with light of the porous silicon formed by anodization in the surface region of the silicon substrate 101 as shown in FIG. 33, the following problems are encountered.
That is, the diameter and depth of the micro-pore 102 formed by anodization are difficult to control. In addition, the configuration of the micro-pore 102 is complicated and the distribution of its wall thickness is extremely random. As a result, if etching is intensely performed in order to reduce the wall thickness, the wall portions may be partially torn and peeled off the substrate. Moreover, since the distribution of the wall thickness is random, the quantum size effects are not generated uniformly over the whole wall portions, so that light emission with a sharp emission spectrum cannot be obtained. Furthermore, the wall surface of the micro-pore in the porous silicon readily adsorbs molecules and atoms during anodization, due to its complicated configuration. Under the influence of the atoms and molecules attached to the surface of the silicon, the resulting optical element lacks the capability of reproducing a required emission wavelength and its lifespan is also reduced.
On the other hand, with the development of the present information-oriented society, a semiconductor apparatus in which a semiconductor integrated circuit is disposed has presented an increasing tendency toward the personalization of advanced info-communication appliances with large capacities. In other words, there has been a demand for appliances which enable advanced information transmission to and from a hand-held computer or cellular phone. To meet the demand, it is required to not only enhance the performance of the conventional semiconductor apparatus, which processes only electric signals, but also implement a multi-function semiconductor apparatus which processes light, sounds, etc., as well as electric signals. FIG. 34 shows the cross sectional structure of a three-dimensional integrated circuit system that has been developed in order to satisfy the requirements. Such a three-dimensional integrated circuit system is expected to surmount the miniaturization limit inherent in the conventional two-dimensional integrated circuit system as well as improve and diversify functions to be performed. In the drawing, a PMOSFET 110a consisting of a source 103, a drain 104, a gate oxide film 105, and a gate 106 is formed in the surface region of an n-well 102, which is formed in a p-type silicon substrate 101a as a first layer. In the surface region of the first-layer silicon substrate 101a are formed semiconductor apparatus including an NMOSFET 110b consisting of the source 103, drain 104, gate oxide film 105, and gate 106. There are also formed a connecting wire 107 between the source and drain regions and an inter-layer insulating film 108 for covering each region, which has been flattened. On the inter-layer insulating film 108 is formed a second-layer silicon substrate 101b made of single-crystal silicon. On the second-layer silicon substrate 101b are also formed semiconductor apparatus such as the PMOSFET 110a and NMOSFET 110b, similarly to the semiconductor apparatus on the above first-layer silicon substrate 101a. The semiconductor apparatus in the first layer and the semiconductor apparatus in the second layer are electrically connected via a metal wire 109 (see, e.g., "Extended Abstracts of 1st Symposium on Future Electron Devices," p.76, May 1982).
However, such a three-dimensional integrated circuit system has the following problems. The wire 109 is formed by a deposition method in which, after a contact hole was formed, a wiring material is deposited and buried in the contact hole. Since the resulting contact hole becomes extremely deep, deficiencies such as an increase in resistance value and a break in wiring are easily caused by a faulty burying of the wiring material, resulting in poor reliability. With such problematic manufacturing technology, it is difficult to implement a three-dimensional integrated circuit system which can be used practically. In particular, it is extremely difficult to implement an integrated circuit system in more than three dimensions.